Ralf Hildebrandt <Ralf-Hildebrandt@gmx.de> writes:

>> A task only updates its outputs (ports) when it completes.
>
> I was guessing that this does actually happen, but I was not sure
> about it. Thank you for clarification.

If your tool supports SystemVerilog, you may also use ref-ports, which
pass signals by reference rather than by value.

Kind regards
Marcus
--
DOULOS Developing Design Know http://www.doulos.com/

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.