Ralf Hildebrandt <Ralf-Hildebrandt@gmx.de> writes:
>> A task only updates its outputs (ports) when it completes.
> I was guessing that this does actually happen, but I was not sure
> about it. Thank you for clarification.
If your tool supports SystemVerilog, you may also use ref-ports, which
pass signals by reference rather than by value.
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