I am facing the problem of modeling a task with a delay (e.g. #1000
and some signal assignments in it. (The purpose is pure testbench
behavior.) The behavior I get is not as expected. Signals seem to be
updated only at the end of the task.
A minimal example is attached to the posting in <task_define.v>. In all
examples 2 signals are are sequentially set using delay statements
. 2 tasks are included in this example - one using blocking- the
other using non-blocking signal assignments. Both have different and
To make clear, what I really want to have, an example using a macro
(`define) is included in <task_define.v> too. Using the macro I get the
behavior I want to have. But my question is: What I am doing wrong using
tasks for this purpose?
Furthermore I attached <procedure.vhd>. I apologize for posting VHDL
code in this Verilog group, but the problem arises while translating
code from VHDL to Verilog. The VHDL code has the same behavior as the
Verilog macro and this is what I want to have.
Tasks in general can handle sequential statements using e.g.
"@posedge(clk)". (See the examples in
<http://www.asic-world.com/verilog/task_func1.html>.) But what about
Thanks in advance